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never stop thinking. microcontrollers data sheet, v1.3, dec. 2000 c505ca-4rc step bb 8-bit single-chip microcontroller (bare die delivery)
edition 2000-12 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2000. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
microcontrollers data sheet, v1.3, dec. 2000 never stop thinking. c505ca-4rc step bb 8-bit single-chip microcontroller (bare die delivery)
controller area network (can): license of robert bosch gmbh c505ca-4rc (bare die delivery) revision history: 2000-12 v1.3 previous version: v1.2, v1.1 page subjects (major changes since last revision) 14 reference of data sheet version is updated we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
data sheet 5 v1.3, 2000-12 c505ca-4rc 8-bit single-chip microcontroller c500 family advance information ? fully compatible to standard 8051 microcontroller superset of the 8051 architecture with 8 datapointers up to 20 mhz operating frequency ? 375 ns instruction cycle time @16 mhz ? 300 ns instruction cycle time @20 mhz (50% duty cycle) on-chip program memory (with optional memory protection) ? 32k byte on-chip mask rom ? alternatively up to 64k byte external program memory 256 byte on-chip ram 1k byte on-chip xram (more features on next page) figure 1 c505ca-4rc functional units oscillator watchdog timer c500 8-bit usart i/o i/o 8 digit. i/o i/o ram xram on-chip emulation support module timer 2 watchdog timer 8 analog inputs / full-can controller 8 datapointers i/o (2-bit i/o port) port 0 port 1 port 2 port 4 port 3 a/d converter (10-bit) 256 byte program memory 0 timer 1 core c505ca-4rc: 32k byte rom 1k byte c505ca-lc: romless
c505ca-4rc step bb data sheet 6 v1.3, 2000-12 features (continued) : 32 + 2 digital i/o lines ? four 8-bit digital i/o ports ? one 2-bit digital i/o port (port 4) ? port 1 with mixed analog/digital i/o capability three 16-bit timers/counters ? timer 0 / 1 (c501 compatible) ? timer 2 with 4 channels for 16-bit capture/compare operation full duplex serial interface with programmable baudrate generator (usart) full can module, version 2.0 b compliant ? 256 register/data bytes located in external data memory area ? 1 mbaud can baudrate when operating frequency is equal to or above 8 mhz ? internal can clock prescaler when input frequency is over 10 mhz on-chip a/d converter ? up to 8 analog inputs ? 10-bit resolution twelve interrupt sources with four priority levels on-chip emulation support logic (enhanced hooks technology tm 1) ) programmable 15-bit watchdog timer oscillator watchdog fast power on reset power saving modes ? slow-down mode ? idle mode (can be combined with slow-down mode) ? software power-down mode with wake up capability through p3.2/int0 or p4.1/ rxdc pin temperature ranges: sab-c505 versions t d = 0 to 70 c saf-c505 versions t d = -40 to 85 c sak-c505 versions t d = -40 to 125 c saa-c505 versions t d = -40 to 150 c 1) ?enhanced hooks technology? is a trademark and patent of metalink corporation licensed to infineon technologies.
c505ca-4rc step bb data sheet 7 v1.3, 2000-12 ordering information table 1 bare die ordering information type ordering code wafers comments SAK-C505CA-LC tbd whole/sawn 8-bit microcontroller with temperature range: -40 c to +125 c (max. operating frequency: 20 mhz with 50% duty cycle) saa-c505ca-lc tbd whole/sawn 8-bit microcontroller with temperature range: -40 c to +150 c (max. operating frequency: 20 mhz with 50% duty cycle) sak-c505ca-4rc tbd whole/sawn 8-bit microcontroller with 32k bytes rom temperature range: -40 c to +125 c (max. operating frequency: 20 mhz with 50% duty cycle) saa-c505ca-4rc tbd whole/sawn 8-bit microcontroller with 32k bytes rom temperature range: -40 c to +150 c (max. operating frequency: 20 mhz with 50% duty cycle) note: the ordering codes for the mask-rom versions (dxxxx extension) are defined for each product after verification of the respective rom code. note: versions for the temperature range 0 c to 70 c (sab-c505) and -40 c to 85 c (saf-c505) are available on request.
c505ca-4rc step bb data sheet 8 v1.3, 2000-12 introduction the c505ca-xc derivatives, which refer to c505ca-4rc and c505ca-lc in this document, are high performance derivatives of the infineon c500 family of 8-bit microcontrollers. the c505ca-xc derivatives are fully compatible to the standard 8051 microcontroller. additionally the c505ca-xc provides extended power save provisions, on-chip ram, 1k byte xram, on-chip rom, 10-bit a/d converter, and rfi related improvements. figure 2 logic symbol port 0 8-bit digital i/o port 1 8-bit digital i/o / port 2 8-bit digital i/o port 3 8-bit digital i/o xtal1 xtal2 reset ea ale psen v aref v dd v ss v agnd 8-bit analog inputs port 4 2-bit digital i/o c505ca-4rc c505ca-lc
c505ca-4rc step bb data sheet 9 v1.3, 2000-12 pad configuration figure 3 c505ca-4rc pad configuration (top view) c505ca-4rc pad 1 pad 11 pad 28 pad 38 pad 12 pad 27 pad 39 pad 49 x y 0.0 0.0
c505ca-4rc step bb data sheet 10 v1.3, 2000-12 table 2 pad definition and functions symbol pad num. in/ out (i/o) position [ m] function xy p1.5 1 i/o 453 0 port 1 general input/output (quasi-bidirectional)/ analog input channel 5 / timer 2 external reload / trigger input p1.6 2 i/o 753 0 port 1 general input/output (quasi-bidirectional)/ analog input channel 6 / system clock output p1.7 3 i/o 1053 0 port 1 general input/output (quasi-bidirectional)/ analog input channel 7 / counter 2 input reset 4 i 1284 0 reset input p3.0 5 i/o 1451 0 port 3 general input/output (quasi-bidirectional)/ receiver data input (asynch.) or data input/ output (synch.) of serial interface p4.0 6 i/o 1796 0 port 4 general input/output (quasi-bidirectional)/ transmitter output of can controller p3.1 7 i/o 2012 0 port 3 general input/output (quasi-bidirectional)/ transmitter data output (asynch.) or clock output (synch.) of serial interface p3.2 8 i/o 2201 0 port 3 general input/output (quasi-bidirectional)/ external interrupt 0 input / timer 0 gate control input p3.3 9 i/o 2586 0 port 3 general input/output (quasi-bidirectional)/ external interrupt 1 input / timer 1 gate control input p3.4 10 i/o 2886 0 port 3 general input/output (quasi-bidirectional)/ timer 0 counter input p3.5 11 i/o 3547 0 port 3 general input/output (quasi-bidirectional)/ timer 1 counter input p3.6 12 i/o 3991 484 port 3 general input/output (quasi-bidirectional)/ wr control output p3.7 13 i/o 3991 778 port 3 general input/output (quasi-bidirectional)/ rd control output xtal2 14 o 3991 1028 output of the inverting oscillator amplifier.
c505ca-4rc step bb data sheet 11 v1.3, 2000-12 xtal1 15 i 3991 1193 input to the inverting oscillator amplifier and input to the internal clock generator circuits. nc 16 - 3991 1355 not connected v ss 17 - 3991 1480 ground (0v) v ss 18 - 3991 1605 ground (0v) v ss 19 - 3991 1730 ground (0v) v dd 20 - 3991 1904 power supply (+5v) v dd 21 - 3991 2029 power supply (+5v) v dd 22 - 3991 2155 power supply (+5v) p2.0 23 i/o 3991 2289 port 2 general input/output (quasi-bidirectional)/ high-order address byte line a8 p2.1 24 i/o 3991 2423 port 2 general input/output (quasi-bidirectional)/ high-order address byte line a9 p2.2 25 i/o 3991 2664 port 2 general input/output (quasi-bidirectional)/ high-order address byte line a10 p2.3 26 i/o 3991 2980 port 2 general input/output (quasi-bidirectional)/ high-order address byte line a11 p2.4 27 i/o 3991 3295 port 2 input/output (quasi-bidirectional)/ high-order address byte line a12 p2.5 28 i/o 3537 3739 port 2 general input/output (quasi-bidirectional)/ high-order address byte line a13 p2.6 29 i/o 3165 3739 port 2 general nput/output (quasi-bidirectional)/ high-order address byte line a14 p2.7 30 i/o 2785 3739 port 2 general input/output (quasi-bidirectional)/ high-order address byte line a15 psen 31 o 2505 3739 program store enable ale 32 o 2186 3739 address latch enable p4.1 33 i/o 1886 3739 port 4 general input/output (quasi-bidirectional)/ receiver input of can controller ea 34 i 1588 3739 external access enable table 2 pad definition and functions symbol pad num. in/ out (i/o) position [ m] function xy
c505ca-4rc step bb data sheet 12 v1.3, 2000-12 p0.7 35 i/o 1327 3739 port 0 general input/output (open-drain)/ multiplexed low-order address and data bus line a7/d7 p0.6 36 i/o 1078 3739 port 0 general input/output (open-drain)/ multiplexed low-order address and data bus line a6/d6 p0.5 37 i/o 744 3739 port 0 general input/output (open-drain)/ multiplexed low-order address and data bus line a5/d5 p0.4 38 i/o 444 3739 port 0 general input/output (open-drain)/ multiplexed low-order address and data bus line a4/d4 p0.3 39 i/o 0 3295 port 0 general input/output (open-drain)/ multiplexed low-order address and data bus line a3/d3 p0.2 40 i/o 0 2936 port 0 general input/output (open-drain)/ multiplexed low-order address and data bus line a2/d2 p0.1 41 i/o 0 2586 port 0 general input/output (open-drain)/ multiplexed low-order address and data bus line a1/d1 p0.0 42 i/o 0 2322 port 0 general input/output (open-drain)/ multiplexed low-order address and data bus line a0/d0 v aref 43 - 0 2078 reference voltage for the a/d converter. v agnd 44 - 0 1878 reference ground for the a/d converter. p1.0 45 i/o 0 1652 port 1 general input/output (quasi-bidirectional)/ analog input channel 0 / interrupt 3 input / capture/compare channel 0 i/o p1.1 46 i/o 0 1370 port 1 general input/output (quasi-bidirectional)/ analog input channel 1 / interrupt 4 input / capture/compare channel 1 i/o table 2 pad definition and functions symbol pad num. in/ out (i/o) position [ m] function xy
c505ca-4rc step bb data sheet 13 v1.3, 2000-12 note: all v ss pads and all v dd pads must be connected to the system ground and the power supply, respectively. the pad definitions and locations in this table are only valid for the indicated device and design step. handling of unconnected pads signal input stages may generate undesired switching noise and cross-current when left open. respect the following precautions for unconnected (not bonded) pads: 1) avoid to set unconnected p1 pad as analog input if left open. however, p1 is set as digital i/o by default after reset. p1.2 47 i/o 0 1129 port 1 general input/output (quasi-bidirectional)/ analog input channel 2 / interrupt 5 input / capture/compare channel 2 i/o p1.3 48 i/o 0 776 port 1 general input/output (quasi-bidirectional)/ analog input channel 3 /interrupt 6 input / capture/compare channel 3 i/o p1.4 49 i/o 0 453 port 1 general input/output (quasi-bidirectional)/ analog input channel 4 table 3 precautions for unconnected pads pad type recommended action related pads power supply always connect! v dd , v ss , v aref , v agnd standard i/o pads(except p0) can be left p1 1) , p2, p3, p4 port 0 set the corresponding pad latches to ? 0 ? s p0 required control lines always connect! reset, xtal1,ea optional control lines can be left open ale, psen , xtal2 table 2 pad definition and functions symbol pad num. in/ out (i/o) position [ m] function xy
c505ca-4rc step bb data sheet 14 v1.3, 2000-12 functional description as the standard packaged devices are made from this silicon the c505ca-xc dies provide exactly the same functionality and behaviour. also the dc characteristics and ac characteristics are compatible with those of the packaged devices. for a description of the functionality and the dc and ac parameters please refer to the following documents (or later versions thereof): c505/c505c/c505a/c505ca data sheet 2000-12 c505/c505c user ? s manual 08.97 c505a/c505ca user ? s manual 09.97 (addendum to c505/c505c)
c505ca-4rc step bb data sheet 15 v1.3, 2000-12 figure 4 block diagram port 0 8-bit digit. i/o port 2 8-bit digit. i/o port 3 8-bit digit. i/o port 0 port 1 port 2 port 3 osc & timing cpu timer 0 timer 1 timer 2 usart xtal1 xtal2 reset ale psen ea vss v dd oscillator watchdog a/d converter (10-bit) s&h mux v agnd v aref port 1 8-bit digit. i/o / 8-bit analog in rom xram 256 byte ram emulation support logic programmable watchdo g timer full-can controller 256 byte reg./dat a interrupt unit 8 datapointers port 4 2-bit digit. i/o port 4 1k byte 32k byte baudrate generator
c505ca-4rc step bb data sheet 16 v1.3, 2000-12 absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage of the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for longer periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. parameter symbol limit values unit notes min. max. storage temperature t st ? 65 150 c ? voltage on v dd pins with respect to ground ( v ss ) v dd ? 0.5 6.5 v ? voltage on any pin with respect to ground ( v ss ) v in ? 0.5 v dd + 0.5 v ? input current on any pin during overload condition ? 10 10 ma ? absolute sum of all input currents during overload condition | 100 ma | ma ? power dissipation p diss 1w ?
c505ca-4rc step bb data sheet 17 v1.3, 2000-12 operating conditions the following operating conditions must not be exceeded in order to ensure correct operatinon of the c505ca-xc. all parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. operating conditions parameter symbol limit values unit notes min. max. supply voltage v dd 4.25 5.5 v active mode 2 5.5 v powerdown mode ground voltage v ss 0 v reference voltage temperature of the bottom side of the die c ? sab-c505 t d 070 saf-c505 t d -40 85 sak-c505 t d -40 125 saa-c505 t d -40 150 analog reference voltage v aref 4 v dd + 0.1 v ? analog ground voltage v agnd v ss ? 0.1 v ss + 0.2 v ? analog input voltage v ain v agnd -0.2 v aref +0.2 v ? xtal clock f osc 220 (with 50% duty cycle) mhz ?
c505ca-4rc step bb data sheet 18 v1.3, 2000-12 storage conditions the c505ca-xc dies may be stored for a certain time under the conditions described below. power supply currents the power supply currents for the bare die are compatible with those of the packaged devices with the following exceptions: the maximum power down current (i pd ) for bare die is: i pd max. = 35 ua table 4 bare die storage conditions and duration packing environment temperature rel. humidity storage time vacuum pack air 15...30 c < 60 % < 4 months
c505ca-4rc step bb data sheet 19 v1.3, 2000-12 bare die outline figure 5 bare die outline 0.38 3.983 (including scribeline) 4.235 (including scribeline) dimensions in mm 0.090 0.090 0.125 x y 0,0 min typical 4.125 (excluding scribeline) 3.873 (excluding scribeline)
c505ca-4rc step bb data sheet 20 v1.3, 2000-12 the wafers are glued to a plastic tape which is fixed within a plastic ring (see figure below). wafers can be shipped in one piece or sawn into individual dies. table 5 wafer characteristics item characteristic chips per wafer 820 metallization layers 2 metallization material aicu metallization thickness met1: 450 nm, met2: 800 nm metallization barrier material ti/tin metallization isolation flow-fill metallization material on pads aicu (ai 99.5% - cu 0.5%) passivation si-oxide (310 nm) + si-nitride (510 nm) backside metallization none (silicon) inkdot diameter 1.0-1.3 mm (typical)
c505ca-4rc step bb data sheet 21 v1.3, 2000-12 wafer outline figure 6 wafer outline 152.4 (6 ? ) dimensions in mm 210 230 plastic frame plastic tape wafer
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